OpenLane/OpenRoad tool flow and “improve” the picorv32a design

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OpenLane/OpenRoad tool flow and “improve” the picorv32a design. Picorv32a is a 32-bit RISC-V microprocessor. Digital designs are primarily evaluated by “PPA” which includes: Power(dynamic and leakage) Performance (clock period orfrequency) Area (silicon chip size) Our goal of this assignment is to measure these metrics after design “signoff” (which is post-routing and extraction). We are going to compare everyone’s design quality to see the Pareto curves. It is also expected that each design should be DRC clean and LVS should match. Tutorial Read through the very brief tutorial to run a design. We will also give an in depth tutorial in class. Baseline PPA Start by running the picorv32a design in OpenLane: ./flow.tcl -design picorv32a -tag MYRUN Depending on the performance of your computer, this could take 5-30 minutes. The main results that you want are in designs/picorv32a/runs/MYRUN/reports/signoff. Power: *-rcx_sta.power.rpt (Note, the step number may change with OpenLane versions.) Performance: *-rcx_sta.max.rpt (Note, the step number may change with OpenLane versions.) Die Area: Found in yourreports/metrics.csv file. You an also see the baseline results for each stage in the appropriate directory otherthan signoff. For example, placement will have the post-placementresults,routing will have the post-routing results (but without parasitic extraction), etc. 5/16/23, 12:54 PM HW2: OpenLane | CSE 122/222A Spring 2023 https://vlsida.github.io/cse122-222a-s23/hw2/hw2.html 2/3 Improving your design This portion of the homework is intentionally open ended. Your goal is to improve power, performance and area as much as you can. Sometimes, one might make the other worse, so you should use yourjudgement if it is worth it! You will need to look through the options forthe different phases of the design and see what might give you improvement. You can also look at the results of your design to see the impact on it if there are problems. Note, the “baseline” metrics are: Power: 0.0205 Watts (2.05e-02 in scientific notation) Performance: 24 ns (clock period) Die Area: 0.215 mm^2 If you have a significantly differentresult, something might be wrong or you might be looking at the wrong reports! You should examine the options for each stage of the design flow in the OpenLane Documentation and the OpenLane Reference Manual and see what might be relevent. In particular, the Hardening Macros section is the relevent, but also the parameters for each of the design flow stages in the reference manual. Area Area needed depends on the area of the standard cells as well as additional area forrouting to successfully complete. The default floorplan uses 40% area utilization meaning that 60% is blank space for easierrouting. You can play with decreasing this, but decreasing it too far will result in routing congestion and an unroutable design. There are other parameters, however, that might help with congestion during placement. Performance Performance is trickierthan area, but there is also a lot left on the table in the default settings. In the config.json file, the clock period is set to 24 ns and can easily be reduced since our baseline design has a lot of slack. How much slack is there and what should you decrease the period to as a start? Note, however, that changing this may change what is the critical path as well as affect your area and power. There are a number of optimizations that can be done during placement and routing such as gate resizing. Which options might be useful to get more performance? It might be useful to look at the critical path and see what dominates the delay. Is it wire or gate dominated, for example? Is the clock skew bad? Power Poweris probably the most complex to directly target. Dynamic poweris related to the gate sizes, total wire capacitance and switching. Leakage is related to the widths of the transistors (and the topologies of the gates). Internal may be related to slew rates of signals where slower slews will cause more internal short-circuit poewr. 5/16/23, 12:54 PM HW2: OpenLane | CSE 122/222A Spring 2023 https://vlsida.github.io/cse122-222a-s23/hw2/hw2.html 3/3 Project maintained by VLSIDA Grading Create a directory called “hw2” in your GitLab repository. In this directory, you should submit a single PDF called hw2.pdf with any written answers. 1. What are your final improved PPA metrics? Please also submit to ourform. 2. Describe the Power breakdown. How many sequential and combinational gates is your design? 3. What is your critical path and why is it critical? For example: How many stages is it? Does it have long wires (show an image of it)? Does it have high fanout? 4. How big is your design? What is your utilization? 5. What is the wirelength of your placement? 6. Where is the maximum congestion in your design? Physically show this in the GUI. 7. What is your maxmum clock skew? How much clock skew is on your critical path? 8. Write a narrative of your approach to improve PPA. What did each option intend to improve and what were the results? 9. Please submit your final final OpenLane configuration in your class reposory as hw2/config.json Extra Credit: Pareto Bounty Power(and technically area) and delay can be traded for each other. Usually, higher power will mean faster and lower power will mean slower. This creates a trade-off curve where you can trade between power and delay. If a design is betterin both power and delay, it is an obvious win. The one design is said to “dominate” the other. Similarly, what if a design is slower and higher power? Would you ever want to use that design? Most definitely not! However, what if a design is betterin delay, but consumes more powerthan another design? It’s not clearif it “is worth it”, so the two options are both considered Pareto optimal or Pareto efficient. Forthis assignment, we will offer a “Pareto bounty” to all Pareto efficient solutions in terms of power and delay. We will compare the results submitted in the Google form and give extra credit to those that are not dominated (i.e., worse power and delay) than another classmate’s solution. This lets people decide to target either delay, power, or both in any portion they want. We will announce the winners in class. There can potentially be many winners! Total: 150 (165 with extra credit)