question archive You are going to design an instruction set architecture and a pipeline implementation of that architecture
You are going to design an instruction set architecture and a pipeline implementation of that architecture
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You are going to design an instruction set architecture and a pipeline implementation of that architecture. The word length is exactly four bytes. Your instructions will be used to do the following benchmark:Input: an array [a1,a2,a3..]
Output; Summation of array
In your processor, there are 128 registers, all registers are 32 bits; 2's complement is assumed. Use 32 bits to represent the constant n and the starting (base) address of array
A. Add more assumptions if you think necessary. In your report, the followings are expected.
1. Table of contents.
2. Definition of your instruction set and state your assumptions in your design.
3. Assembly code for the benchmark above with your own instructions.
4. Datapath and control.
5. Emulation of the following RISC-V instructions: add, sub, addi, ld, sd, and, or, nor, andi, beq, jal, jalr described in page 64 of the text book. For each RISC-V instruction, give the equivalent instruction or a sequence of instructions in your instruction set.
6. Calculation of your cycle time, CPI, instruction count of the benchmark and the total execution time assuming the time delays for individual components are as follows: ALU and adders: 2 ns; register file: 2 ns; memory unit: 2 ns; mux, buffers etc.: 0.
Your design should minimize the execution time of the given benchmark.
