question archive Caches are important to providing a high-performance memory hierarchy to processors

Caches are important to providing a high-performance memory hierarchy to processors

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Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses.

3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253

Question 1.1 For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.

Question 1.2 For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.

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Answer:
A)
The first thing to notice is that since we have one word blocks and no address is repeated then there are zero cache hits. The other way to say this is that this address sequence exhibits no temporal locality.
Addressten   Binarytwo    Tagten     Blockten   Hit/Miss
  3            00000011    0000       3         Miss
  180          10110100    1011       4         Miss
  43           00101011    0010       11        Miss
  2            00000010    0000       2         Miss
  191          10111111    1011       15        Miss
  88           01011000    0101       8         Miss
  190          10111110    1011       14        Miss
  14           00001110    0000       14        Miss
  181          10110101    1011       5         Miss
  44           00101100    0010       12        Miss
  186          10111010    1011       10        Miss
  253          11111101    1111       13        Miss
B)
Addressten   Binarytwo    Tagten     Blockten   Offset     Hit/Miss
3            00000011    0000      1          1          Miss
180          10110100    1011      2          0          Miss
43           00101011    0010      5          1          Miss
2            00000010    0000      1          0          Hit  (brought in from address 3 reference)
191          10111111    1011      7          1          Miss
88           01011000    0101      4          0          Miss
190          10111110    1011      7          0          Hit  (brought in from address 191 references)
14           00001110    0000      7          0          Miss (kicks out 190 and 191)
181          10110101    1011      2          1          Hit  (brought in from address 180 reference)
44           00101100    0010      6          0          Miss      
186          10111010    1011      5          0          Miss
253          11111101    1111      6          1          Miss

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