question archive EE210 LOGIC CIRCUITS DESIGN - LAB#04 Design a circuit that accepts 4-bit binary input and has a single bit binary output
EE210 LOGIC CIRCUITS DESIGN - LAB#04 Design a circuit that accepts 4-bit binary input and has a single bit binary output
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EE210 LOGIC CIRCUITS DESIGN - LAB#04 Design a circuit that accepts 4-bit binary input and has a single bit binary output. The circuit performs the reduction XOR operation. a) Write down the behavioral-Level HDL code. b) Run the code on implementation tab and obtain RTL Level design. c) Write a testbench for your code. Test at Least 6 different input combinations. -To insert testbench use the tabs Project-> New Source-> Verilog Test Fixture -Give any name to your test fixture and apply 6 different input combinations. -Wait #100 simulation seconds between each input combination - You need to run your testbench using simulation tab (not implementation) ALL of your works must be submitted in a single . pdf file. Your . pdf file should contain full-screen snapshot of Verilog code page, RTL Level design page, testbench page and ISIM simulator output page)
