Discuss what happens to CCR bits when there is an overflow.

 

Condition code register has 5 bits, which are set by ALU.

• N bit is set if result of operation in negative (MSB = 1)
• Z bit is set if result of operation is zero (All bits = 0)
• V bit is set if operation produced an overflow . This bit is used only during operations on signed integers. Bit set to 1 if the addition of two like-signed numbers or subtraction of two opposite-signed numbers produces a result that exceeds the 2's complement range of the operand. In other scenarios, the V bit is cleared and set to 0
• C bit is set if operation produced a carry (borrow on subtraction
• X for extend. Useful in multiple precision instructions