You have a PC with a 2 GHz processor, a system bus clocked at 400 MHz, and a 3 Mbps internal cable modem attached to the system bus

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You have a PC with a 2 GHz processor, a system bus clocked at 400 MHz, and a 3 Mbps internal cable modem attached to the system bus. No parity or other error-checking mechanisms are used. The modem has a 64-byte buffer. After it receives 64 bytes, it stops accepting data from the network and sends a data ready interrupt to the CPU. When this interrupt is received, the CPU and OS perform the following actions:

1. The supervisor is called.
2. The supervisor calls the modem's data ready interrupt handler.
3. The interrupt handler sends a command to the modem, instructing it to copy its buffer content to main memory.
4. The modem interrupt handler immediately returns control to the supervisor, without waiting for the copy operation to be completed.
5. The supervisor returns control to the process that was originally interrupted.

When the modem finishes the data transfer, it sends a transfer completed interrupt to the CPU and resumes accepting data from the network. In response to the interrupt, the CPU and OS perform the following actions:

1. The supervisor is called.
2. The supervisor calls the transfer completed interrupt handler.
3. The interrupt handler determines whether a complete packet is present in memory. If so, it copies the packet to a memory region of the corresponding application program.
4. The modem interrupt handler returns control to the supervisor. e. The supervisor returns control to the process that was originally interrupted.

Sending an interrupt requires one bus cycle. A push or pop operation consumes 30 CPU cycles. Incrementing the stack pointer and executing an unconditional branch instruction require one CPU cycle each. The supervisor consumes eight CPU cycles searching the interrupt table before calling an interrupt handler. The data ready interrupt handler consumes 50 CPU cycles before returning to the supervisor.

Incoming packets range in size from 64 bytes to 4096 bytes. The transfer complete interrupt handler consumes 30 CPU cycles before returning to the supervisor if it doesn't detect a complete packet in memory. If it does, it consumes 30 CPU cycles plus one cycle for each 8 bytes of the packet. (See also page 225)

Please show the answers and supporting computations in the provided charts.

Facts For the Project
Device	Clock rate (MHz)	Cycle time (ns)	Width (bytes)	Speed (bytes/sec)
Bus
CPU
Modem buffer (question 1)
Modem buffer (question 2)
Modem speed
Operation		Cycles
Push
Pop
Increment stack pointer
Branch
Supervisor lookup
Data ready interrupt handler
Transfer complete interrupt handler
Interrupt handler memory copy (8 bytes)