Lab 5: NMOS Capacitor Simulation Lab Silvaco Software Background Silvaco is commercial simulation software is very versatile and can be used in a variety of applications

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Lab 5: NMOS Capacitor Simulation Lab Silvaco Software Background Silvaco is commercial simulation software is very versatile and can be used in a variety of applications. For background on how to use this software see the handout attached to the course module Introduction to Silvaco Code The code for running the simulation is shown below. By commenting out certain parts of the code it is possible to simulate a NMOS capacitor under various conditions I. Equilibrium conditions The device we will initially simulate has a Aluminum metal gate, a oxide thickness of 300nm a base region thickness of .5 microns and a Silicon base doping of 1E16 cm-3. Print out the structure file for the NMOS capacitor in equilibrium using the tonyplot software. The structure file contains all the information about the device (electric field, potential, doping ect.). The structure file is shown below. The various colors show the various regions of the device. Using a cutline tool open the structure file. By changing the display parameters you can view the hole concentration, electric field, potential and other things. Display the equilibrium electric field, hole concentration and potential diagrams and using saving screen save a copy of these images. II. Bias conditions The software simulates the device under a bias from -2 to +2 volts. The small signal capacitance is calculated as a function of bias and structure files are saved at accumulation and inversion. Run the software for the initial conditions of oxide thickness and base doping specified in one. Take screen shots of the capacitance vs voltage curve, Electric field vs distance, potential vs distance and hole concentration vs distance for both accumulation and inversion. III Effect of oxide thickness Change the oxide thickness from 300nm to 100nm and repeat part II IV Effect of doping Return the oxide thickness to 300nm. Change the doping concentration from 1E16 to 1E15 and repeat part II. Report From the device structure calculate the Electric Field and Potential at x=0, -tox and Capacitance for doping of 1015 cm-3 and 1016 cm-3 and for thickness of 30nm and 10nm at total of four conditions. Compare your results with the simulated results. Lab 6 NMOS FET Characteristic Curves and Amplifier Objective: The purpose of this lab is to investigate the drain current vs. gate voltage characteristics of an NMOS FET transistor as well as basic amplifier parameters Materials: 100Ω resistor 1K resistor Small signal NMOS transistor (CD4007) Directions: Part I ID vs VGS The drain current vs. gate voltage characteristics of an NMOS transistor can be measure using the analog discovery kit. Transistor is in a dual in line package (CD4007) as a set of NMOS and PMOS devices (see spec sheet). The transistor we will use has it’s drain on pin 7, the gate on pin 6 asnd the source on pin 8. Set up the breadboard with the arbitrary waveform generator output W1 (AWG) attached to the gate terminal of M1. Connect one end of resistor R1 to both the W2 (AWG) which is set to supply a dc voltage Vp supply and the 2+ scope input. Connect the opposite end of resistor R1 to both the drain of M1 and scope inputs 2- and 1+. The source of M1 is connected to ground. The breadboard should look similar to the picture below The dc drain voltage should be set to 5V. The arbitrary waveform generator should be configured for a 1 Hz triangle wave with 2.5 volt amplitude peak-topeak and 2.5 volt offset. The differential scope channel 2 (2+/-) measures the current in the resistor (and in the transistor). Scope channel 1 should be connected to display the output of the waveform generator. The current flowing through the transistor is the voltage difference 2+ and 2- divided by the resistor value (100Ω) using a math channel as before. Using a XY set up Plot the drain current vs. the gate voltage of the transistor (VGS), the plot should look like below No drain current should flow when VGS is less than VTH the threshold voltage of the transistor. The threshold voltage, VTH, can be both positive, for an enhancement mode, and negative, for a depletion mode device. When VGS is greater than VTH, the gate voltage to drain current relationship is quadratic. Now plot the drain current vs. the square of the gate voltage. The line should be straight as seen in the second plot. Part II ID vs VDs Starting with the previous breadboard setup, Set AWG 1 and replace it with W1 taken from the gate terminal. Now place W2 on the gate terminal (in place of W1). The setup is similar to previous experiment. Scope channel 1 is set to display the transistor VDS. The drain voltage is swept using a 2.5 volt peak to peak ramp with an offset equal to 2.5V from the arbitrary waveform generator. VDS is measured by single ended scope input 1+. The drain current is measured by differential scope input 2+/across the 100Ω resistor R1. A stair-step waveform will be needed to drive the gate of the transistor. W2 will need to be a custom waveform, so select "Custom" from the type menu, and then click "New". The custom waveform window will open. Click on the "Values" tab at the top and set values 1-5 as 0, 1, 2, 3, 4, and 5 respectively. Uncheck the normalize box at the bottom left, click "Generate" to the right of that, and then click the "Normalize" icon at the top left of the plot window. You should get the following: Click "OK" once you're done to send it to the waveform generator grid. Set the frequency to 40 Hz, amplitude to 2.5 V, and offset to 2.5 V. You should see this: This time we'll need to use both Waveform Generator channels since we need to generate both stepped and swept voltages at the same time. We'll use channel 2 for the steps and channel 1 for the sweep. Make sure that both channels are checked in the drop down menu to turn on both channels. We will need to sweep the whole range of the AD2 voltage output in the time channel 1 is generating each step voltage. "Simple" should be selected by default for channel 1, so set the parameters on the left side as triangle for type, 240 Hz for frequency, 2.5 V for the amplitude and offset, and then the phase to 270°. You should see this: Select synchronize in the AWG menu. Go to the scope select add XY and you should be able to produce the graph shown Part III Transfer function Vout vs VIn Replace the 100 resistor with a 1K load resistor. Move the scope 2 input to measure Vgs and scope 1 will measure Vout. Generate the following curve. Part IV Common Source Amplifier Set using W1 on the gate set a sine wave offset by 2v and an amplitude of 100mv. Using W2 set the drain voltage to 5V. Measure the ac component ID. ID/100mV is the transconductance. Change the input offset voltage to 2.5V what is the value of transconductance. Change the input offset voltage to 1.5 volts what is the value of transconductance. Set the amplitude of the sine wave to zero on the gate. Using W2 set apply a since wave of mag 100mv with a offset of 4V. Measure the ac component of ID. ID/100mv is the output conductance. Changes the offset to 1V repeat the measurement. Report 1. Calculate the threshold voltage for the transistor. 2. Experimentally determine the VSD saturation voltage for the gate bias voltages used. 3. Label to various regions of the transfer function on the experimental graph. 4. Calculate the transconductance and output conductance for the amplifier of part 4 (load resistance of 1K).